Scope-of-Work

	Project: HITL FPGA Implementation T_HITL
	status: na tags: tutorial style: discreet layout: clean_l links incoming: HL_001, HL_002
	DescriptionFlat-Sat (Image) The FPGA needs to implement two UART interfaces over external RS422 and LVDS ICs, which are controllable by host software over PCI-Express

        %%{init: {'theme':'neutral'}}%%
flowchart LR
    host[Host SW] <==> a[PCIe2MM Bridge]
    subgraph Custom Hardware
        subgraph FPGA
            a[PCIe2MM Bridge] <==> b[**Memory Map**]
            subgraph **Customer Request**
                b[**Memory Map**] <==> c[**UART CH.1**]
                b[**Memory Map**] <==> d[**UART CH.2**]
            end
        end
    c[**UART CH.1**] <==> e[UUT]
    d[**UART CH.2**] <==> f[UUT]
    end
e[RS422 IC] <==> g[UUT]
f[LVDS IC]  <==> g[UUT]
    

The High-Level / Key section captures the customer’s high-level needs in requirements format.

Note

The Scope-of-Work is a general description of what the customer is asking for - this information is captured in a Sphinx-Needs “object” and is the root of the Traceability Diagram