Low-Level / Derived¶
ID |
Title |
Tags |
Status |
|---|---|---|---|
UART Baud Rate (CH.1) |
comms; LL |
open |
|
UART Frame Format (CH.1) |
comms; LL |
open |
|
UART Frame Synchronization (CH.1) |
comms; LL |
open |
|
UART Control/Status (CH.1) |
comms; LL |
open |
|
UART Baud Rate (CH.2) |
comms; LL |
closed |
|
UART Frame Format (CH.2) |
comms; LL |
closed |
|
UART Frame Synchronization (CH.2) |
comms; LL |
closed |
|
UART Control/Status (CH.2) |
comms; LL |
in-progress |
Note
Low-Level Requirements are most applicable to the design team, where the technical requirements, specification, and verification criteria is established and performed with traceability to the high-level (customer) requirements
Derived Requirements could be Key Requirements which needed further elaboration to be useful from a digital design / verification perspective
At this level, Specifications are black-box behavioral models for requirements that design teams design to, and verification teams reference to build their simulation harnesses and test cases
A Traceability Diagram is helpful for visualizing the hierarchy of requirements
Low-Level / Derived (Full Descriptions)¶
The FPGA shall provide a UART w/ programmable baud rate for the following rates:
Bit period, T, specified for each baud rate:
Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates the UART achieves a bit period within a +/- 5% for each baud rate |
The FPGA shall provide a UART w/ a frame format defined by the following:
For a UART frame with 8-bit data payload = 0x3: Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates correct frame format over 100 consecutive loopback transmissions |
The FPGA shall provide a synchronization signal that aligns to the UART frame with a +/- 2ms margin For a UART frame with 8-bit data payload = 0x3: Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates the frame synchronization is within the +/- 2ms margin |
The FPGA shall provide 32-bit control/status registers which are aligned on a 4-byte boundary for the UART interface, which is accessible by host software over PCI-Express Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates register writes/reads occur on a 4-byte boundary starting from the base address |
The FPGA shall provide a UART w/ programmable baud rate for the following rates:
Bit period, T, specified for each baud rate:
Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates the UART achieves a bit period within a +/- 5% for each baud rate |
The FPGA shall provide a UART w/ a frame format defined by the following:
For a UART frame with 8-bit data payload = 0x3: Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates correct frame format over 100 consecutive loopback transmissions |
The FPGA shall provide a synchronization signal that aligns to the UART frame with a +/- 2ms margin For a UART frame with 8-bit data payload = 0x3: Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates the frame synchronization is within the +/- 2ms margin |
The FPGA shall provide 32-bit control/status registers which are aligned on a 4-byte boundary for the UART interface, which is accessible by host software over PCI-Express Analysis: verified by simulation Verification shall be considered complete when simulation demonstrates register writes/reads occur on a 4-byte boundary starting from the base address |