High-Level / Key

Used filter: tags(HL)

ID	Title	Tags	Status
HL_001	UART over RS422	comms; HL	open
HL_002	UART over LVDS	comms; HL	in-progress

Note

High-Level Requirements are the customer requirements which serve as the “handshake” between the customer and the design team about what the product is unambiguously supposed to do

Key Requirements could be requirements that are received from a system specification which need to be flowed down to FPGA requirements proper

Regardless of what nomenclature convention is adopted for a project, either one will likely have flowdown to their complementary requirements in the Low-Level / Derived section

High-Level / Key (Full Descriptions)

Requirement: UART over RS422 HL_001

status: open tags: comms, HL style: discreet links outgoing: T_HITL links incoming: LL_001, LL_002, LL_003, LL_004

DescriptionVerification Method The FPGA shall provide a UART w/ an additional frame-synchronization signal targeting an external RS422 IC which is controllable by software over PCI-Express

Requirement: UART over LVDS HL_002

status: in-progress tags: comms, HL style: discreet links outgoing: T_HITL links incoming: LL_005, LL_006, LL_007, LL_008

DescriptionVerification Method The FPGA shall provide a UART w/ an additional frame-synchronization signal targeting an external LVDS IC which is controllable by software over PCI-Express